1. Field of the Invention
The present invention relates to an array of active devices. More particularly, the present invention relates to an array of active devices and a method for testing an array of active devices with high testing accuracy.
2. Description of the Related Art
The demand for displays is getting greater. Therefore, the industry spares no effort in their research and development. Among various types of displays, the flat panel display is taking over the dominating position because of its superior characteristics such as high picture quality, small foot print, low power consumption, and absence of radiation.
At present, the major types of flat panel display include liquid crystal display (LCD), organic electro-luminescence display (OELD), and plasma display panel (PDP), etc. Among them, the LCD and the OELD are generally driven by active devices to shorten the response time of displays.
Besides, due to the demand for higher resolution and smaller size, the technology of mounting and packaging driver integrated circuits (IC) on display panels has shifted gradually from chip on board (COB) to tape automated bonding (TAB), and afterwards to chip on glass (COG), which features fine pitches between the pins of integrated circuits.
FIG. 1 is a schematic diagram showing a display panel driven by active devices using the conventional COG technology. Please refer to FIG. 1, the display panel 100 driven by active devices comprises the display area 102 and the peripheral area 104. The display area 102 comprises a plurality of scan lines 112, a plurality of data lines 114, and a plurality of pixel units 116 connected to the scan lines 112 and the data lines 114. The peripheral area 104 comprises a plurality of gate drivers 120 and a plurality of data drivers 130. The gate drivers 120 are electrically connected to the scan lines 112, while the data drivers 130 are electrically connected to the data lines 114. In other words, the scan lines 112 and the data lines 114 are driven by the gate drivers 120 and the data drivers 130, respectively.
In the fabrication process of active flat panel display, the completion of the display panel 100 in FIG. 1 is usually followed by a circuit test to verify whether there are any defects generated on the circuit of the display panel 100 during the fabrication process. FIG. 2 shows the conventional deployment of test pads for testing the display panel 100 in FIG. 1. Please refer to FIG. 1 and FIG. 2, apart from the gate drivers 120 and the data drivers 130, the peripheral area 104 of the display panel 100 further comprises a plurality of test pads 140 for circuit testing. The test pads 140 are connected to the receiving pads 132 of the data drivers 130 (or the gate drivers 120), respectively.
In the circuit test mentioned above, the tester uses the probe 108 to send test signals to the test pads 140. The test signals will be provided to the display area 102 via the test pads 140 to test the pixel units 116 within the display area 102. For saving space in medium-size and small-size display panels, the receiving pads 132 of the gate drivers 120 and the data drivers 130 are arranged in an interleaved way on the display panel, as shown in FIG. 2.
Furthermore, for increasing the resolution of current medium-sized and small-sized display panels, the sizes of and the distances between the test pads 140 and the receiving pads 132 are getting minimized. Taking a 5.5-inch display panel for example, the area of a test pad 140 is about 36 micrometers by 150 micrometers, and the distance d is about 24 micrometers. For test pads of such size, the probe 108 used in the test has to be smaller and more accurate. However, such probes are expensive and will increase the cost of testing the display panel 100.
Besides, as the distance d between the test pads 140 is getting smaller, the accuracy of the test is bound to deteriorate because the probe 108 may probe into wrong positions and adjacent test signals may interfere with one another during the circuit test.